1. Field
Example embodiments relate to semiconductor memory devices, and more particularly, semiconductor memory devices having a source voltage bit line pre-charge scheme.
2. Description of Related Art
In related art semiconductor memory devices, a source voltage VDD or VDD/2 is used as a bit line pre-charge voltage. Such related art semiconductor memory devices usually use a half VDD bit line pre-charge scheme in which VDD/2 is used as a bit line pre-charge voltage and potential variations of bit lines are symmetrical during a read operation regardless of a data value stored in a memory cell. However, as an operating voltage (a source voltage VDD) of a semiconductor memory device is gradually lowered, a threshold voltage of a cell transistor of a memory cell increases. As a result, accurately detecting data in semiconductor memory devices having a half VDD bit line pre-charge scheme becomes more difficult. Moreover, it is relatively difficult to lower a threshold voltage of a transistor, which configures a sense amplifier for detecting and amplifying a voltage of a bit line pair to suppress and/or prevent a leakage current. For this reason, a full VDD bit line pre-charge scheme in which VDD is used as a bit line pre-charge voltage and influence of a threshold voltage of a sense amplifying transistor is relatively small is preferred.